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| 1. general description the pca9521 is a monolithic bipolar integrated circuit for bus buffering in applications including i 2 c-bus, smbus, pmbus, and other s ystems based on similar principles. the buffer extends the bus load limit by buffering both the scl and sda lines. it supports up to 400 pf loads on each side of the buffe r at 400 khz. higher capacitance is supported at lower speeds, and lower capacitance at higher speeds up to 1 mhz. the enable function allows sections of the bus to be isolated. individual parts of the system can be brought on-line successively. this means a controlled start-up using a diverse range of components, operating spee ds and loads is eas ily achieved. systems employing removable components on a back-plane (e.g., telecommunications racks) can use the enable pin and the high-impedance ports on power-down to safely install and remove components in active systems. bus level translation between a very wide range of bus voltages, from 1.8 v to 10 v, is supported. this featur e provides enormous flexibility in interfacing systems of different technologies. the unique operation of the pca9521 provides one of the fastest response times of such bidirectional buffers, ensuring any glitches (common to other buffers) are kept well within the 50 ns i 2 c-bus specification. additionally, it do es this without the need for ?rise-time accelerators? which, combined with low noise margins, may cause glitches outside of the i 2 c-bus specification. 2. features and benefits ? dual, bidirectional unity gain buffer ? fast switching times allow op eration in excess of 1 mhz ? supports i 2 c-bus (standard-mode and fast-mode), smbus (standard and high power mode), pmbus and ipmb ? enable allows bus segments to be disconnected ? low standby current when not enabled ? application/removal of po wer to ic will not interfere with other bus activity ? 6 ma (static) pull-down capability supp orts a wide range of bus standards ? low noise susceptibility ? low input-output offset voltage ? threshold and offset parameters allow the connection of several devices in series ? bus levels independent of supply voltage ? operating voltages from 2.7 v to 5.5 v ? wide range of bus voltages from 1.8 v to 10 v pca9521 fast dual bidirectional bus buffer rev. 1 ? 22 august 2011 product data sheet
pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 2 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer ? level shifting between different bus voltages ? achieves superior response times without the need for rise time accelerators ? esd protection exceeds 2 kv hbm per jesd22-a114 and 500 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma 3. applications ? power management systems ? telecommunications systems including atca ? desktop and portable computers including raid ? building automation ? tv/projector/monitor interconnection ? game consoles/boxes ? compactpci ? medical systems ? gaming machine networks ? backplane management/interconnect 4. ordering information table 1. ordering information type number topside mark package name description version pca9521d pca9521 so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 PCA9521DP 9521 tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 3 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer 5. block diagram 6. pinning information 6.1 pinning 6.2 pin description fig 1. block diagram pca9521 1en sa1 sb1 2 7 sa2 sb2 3 6 v cc 8 4 gnd 1.8 v to 10 v 2.7 v to 5.5 v r3 1.8 v to 10 v r4 scl sda 1.8 v to 10 v r1 1.8 v to 10 v r2 scl sda enable (up to 10 v) 002aaf280 fig 2. pin configuration for so8 fig 3. pin configuration for tssop8 pca9521d en v cc sa1 sb1 sa2 sb2 gnd n.c. 002aaf278 1 2 3 4 6 5 8 7 PCA9521DP en v cc sa1 sb1 sa2 sb2 gnd n.c. 002aaf279 1 2 3 4 6 5 8 7 table 2. pin description symbol pin description en 1 enable sa1 2 buffer a, port 1 (scl output [1] ) sa2 3 buffer a, port 2 (scl input [1] ) gnd 4 supply ground n.c. 5 not connected sb2 6 buffer b, port 2 (sda input [1] ) sb1 7 buffer b, port 1 (sda output [1] ) v cc 8 positive supply pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 4 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer [1] recommended i 2 c-bus orientation for device family compatibility. 7. functional description refer to figure 1 ? block diagram ? . 7.1 v cc , gnd ? supply pins the power supply voltage for the pca9521 may be any voltage in the range 2.7 v to 5.5 v. the threshold level below which the output will begin to match the input is 33 % of v cc . hence, the operating voltage should be chosen with the required bus voltage, switching threshold, and noise margins, in mind. 7.2 sa1, sa2, sb1, sb 2 ? buffer inputs/outputs the two buffers (sa and sb) are identical and symmetrical. the buffers can be driven from either direction, with the same response. when port 1 of the buffer is being driven low (< 0.3v cc ) by another device on the bus, port 2 will be driven low by the ic to provide the buffered output. the ?input? side is determined by the lowest ex ternally driven signal. therefore if port 1 is externally pulled to v sx1 = 250 mv, and port 2 is externally pulled to v sx2 = 500 mv, the buffer will pull port 2 down furt her such that it becomes v sx2 =v sx1 +v offset . should port 2 subsequently become lower than port 1 by the amount of the offset voltage (v sx2 +v offset pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 6 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer [1] guaranteed by design (not subject to test). timing characteristics [1] t d delay time v cc =5v; v bus =5v; r pu(bus) =1k ? ; c l(ext) = 120 pf; figure 4 -30-ns t f fall time v cc =5v; v bus =5v; r pu(bus) =1k ? ; c l(ext) = 120 pf; figure 4 -15-ns f oper(i2c) i 2 c operating frequency 0 - 400 khz f oper(max) maximum operating frequency 1000 - - khz t d(en-act) enable to active delay time en high to sxx active - 1 - ? s t d(dis-stb) disable to standby delay time en low to sxx disabled - 1.1 - ? s table 4. characteristics ?continued t amb = ? 40 ? c to +85 ? c; voltages are specified with respect to ground (gnd). symbol parameter conditions min typ max unit t amb =25 ? c; v bus(in) = 200 mv. fig 4. timing parameters fig 5. offset voltage, v o ? v i v bus(out) = 500 mv; v cc =2.7v. fig 6. supply current versus ambient temperature fig 7. low-level output current versus ambient temperature 002aaf281 t f t d v bus 33 % v cc time 70 % v sx2 30 % v sx2 sx2 sx1 v sx2 v sx1 50 75 25 100 125 v offset (mv) 0 r pu (k) 010 8 46 2 002aaf325 v cc = v pu = 5 v 7.6 8.4 9.2 i cc (ma) 6.8 t amb (c) ?50 150 100 050 002aaf283 v cc = 5.0 v 3.3 v 11 14 13 12 15 i ol (ma) t amb (c) ?50 150 100 050 002aaf284 pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 7 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer (1) input 33 pf (2) output 120 pf (1) input 33 pf (2) output 120 pf fig 8. rise time (4 ma pull-up) fig 9. fall time (4 ma pull-up) 002aaf285 time (ns) 3.5 voltage (v) horizontal scale = 40 ns/div (1) (2) 2.5 1.5 0.5 ?0.5 4.5 002aaf286 time (ns) 3.5 voltage (v) horizontal scale = 40 ns/div (1) (2) 2.5 1.5 0.5 ?0.5 4.5 pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 8 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer 10. application information 10.1 design considerations figure 10 shows the pca9521 level shifting signals from 1.8 v to 3.3 v at 1 mhz clock speed. the pca9521 has excellent applicat ion to extending loads and providing interfaces to connectors on high speed mi croprocessor cards, well in excess of the fast-mode 400 khz i 2 c-bus specification. rise times are determined simply by the side of the buffer with the slowest rc time constant. figure 11 shows a typical application for the pca9521. the ic can level shift between different bus voltages without the need for ex ternal components. higher bus voltages and currents outside the range of the standard-mode i 2 c-bus specification can be catered for, providing a longer range capab ility and higher noise immunity. the enable pin (en) can be used to interfac e buses of different operating frequencies. when certain bus sections are enabled, the system frequency may be limited by a bus section having a slave device specified onl y to 100 khz. when that bus section is disabled, the slow slave is isolated and th e remaining bus can be run at 400 khz. the timing performance and curren t sinking capability will allow the pca9521 to run well in excess of the 400 khz maximum limit of the fast-mode i 2 c-bus. (1) input 33 pf (2) output 120 pf fig 10. 1.8 v to 3.3 v level shifting at 1 mhz voltage (v) (1) (2) 2.5 1.5 0.5 ?0.5 002aaf287 4.5 time (ns) horizontal scale = 200 ns/div 3.5 pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 9 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer figure 12 shows the pca9521 used in a radial (star) configuration on an advancedtca shelf management controller board (shmc). the pca9521 is highly suited to this and other backplane applications, providing excellent noise margins and i 2 c-bus compliant switching levels. fig 11. pca9521 typical buffer application bus master 400 khz u1 v cc scl sda r1 600 r2 600 sa1 sb1 1.8 v en u2 pca9521 v cc 3.3 v c1 0.01 f sa2 sb2 r3 3.9 k r4 3.9 k 10 v 10 v backplane or cable run sa1 sb1 en u3 pca9521 v cc 5 v c2 0.01 f sa2 sb2 r5 1.1 k r6 1.1 k scl sda u4 v cc 3.3 v slave 100 khz 002aaf288 the system shown here uses fet switches, however a valid alternative is to simply use 24 ? pca9521?s without fet switches. long track runs on the shmc board and backplane can sometimes re sult in high frequency tuned circuits on either side of the pca9521. if your layout is prone to forming such tuned circuits, it is perfectly acceptable to use a ?traditional? damping resi stor (rd) across the pca9521. (1) rra = rise rate accelerator. fig 12. advancedtca style backplane application using pca9521 in a radial shelf manager configuration backplane 002aaf289 pca9522 p required v il = 0.3v cc (max.) = 0.99 v r fru with switching levels compliant with the i 2 c-bus standard fet switches to shmc #2 v max = 0.5 v (picmg3.0) r enables pca9521 rd rra (1) r pca9522 r v ol = v i + 0.08 v v i p fully bused compliant plug-in (hot-insert) shmc module (e.g., amc) pca9521 rd 12 pca9521 isolating bus buffers p r i 2 c-bus alternate implementations pca9521 rd pca9521 rd fet switches r enables example of existing frus built to picmg3.0 r2.0 buffer with rta p required v il = 0.6 v (typ.) r to shmc #2 etc. shmc1 shmc2 ipmb ( 24) total 12 fet switches (4 / pkg.), giving 24 bus outputs pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 10 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer peripheral cards (or fru (field replaceable units)) and backplanes operating at a range of voltages can be interfaced together using a minimum of components. the pca9521 can be teamed with the pca9522 to achieve substantial noise margin gains across a system. multiplexers such as the pca9544a are si mple analog switches which provide no capacitive load isolation between connected branches. figure 14 shows the pca9521 enhancing an i 2 c-bus multiplexer applicat ion, by isolating the load capacitance of each branch. figure 15 and figure 16 show alternate forms of bus multiplexing. similarly, the p82b715 i 2 c-bus extender, which is commonly used for line driver applications, provides a ?10 ? impedance transformation? but does not isolate either side of the buffer. figure 13 shows the pca9521 used to isolate the bus loading due to the p82b715. this greatly simplifies calculation of the pull-ups, increases the total system loading capability in extender applications, will meet the fa st-mode releas e requirement (when pca9521 and p82b715 v cc ?s share a common supply), and ensures the 300 ns rise time requirement can easily be met even if the cable bus rise is relatively slow. buffers are intended to extend total system capacitance above 400 pf, so anticipate high capacitance on each side. when loading on o ne side is small, adding 47 pf is suggested to avoid any waveform ripple, should it occur. pca9521 provides bus isolation and simp lifies calculation of bus rc components. fig 13. pca9521 isolating the standard-mode i 2 c-bus from a p82b715 used as a line driver r1 1.1 k r2 1.1 k 3.3 v 002aaf290 isolated i 2 c-bus scl sda sa1 sb1 en pca9521 v cc sa2 sb2 p82b715 v cc lx ly no pull-up required u1 u2 sx sy r3 r4 5 v long cable run pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 11 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer alternately, using the pca9546a (which allows mu ltiple outputs to be selected) you would simply place a pca9521 on each output on the right-hand side, rather than a single pca9521 on the left-hand side fig 14. pca9521 multiplexer isolation application fig 15. pca9521 bus multiplexer applicatio n driven from a simple logic device 002aaf291 bus master u1 v cc scl sda r1 1.5 k r2 1.5 k sa1 sb1 en u2 pca9521 v cc 5 v sa2 sb2 r3 1.1 k r4 1.1 k 3.3 v scl sda pca9544a v dd sc0 sd0 u3 int[3:0] a0 a1 a2 sc1 sd1 sc2 sd2 sc3 sd3 using the pca9521, up to 400 pf may be connected to each and every bus 0 through bus 3. r1 1.5 k r2 1.5 k 5 v 002aaf292 scl sda sa1 sb1 en pca9521 v cc sa2 sb2 u2 a b 74ls137 v cc y0 y1 u1 y2 y3 c y4 y5 y6 y7 sa1 sb1 en pca9521 v cc sa2 sb2 u3 5 v multiple isolated buses with 400 pf load capacitance each 3-to-8 demultiplexer pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 12 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer 10.2 input to output of fset voltage calculation the offset voltage between the side acting as the output (sxx(out)) and the side acting as the input (sxx(in)) of the pca9521 can be calculated using the relationship given in equation 1 : (1) this calculation is valid for v bus(in) ? 200 mv, as below this point the saturation voltage of the open-collector output driv e transistor will begin to affect the characteristic. input and output voltages are shown in millivolts, v bus (the supply voltage to the bus) is in volts, and r is in ohms. an example calculation for v bus =3.3v, v sa1 = 200 mv, the resistance r pulling up sa2 is 2 k ? , then the voltage on sa2 is typically: (2) this can be compared with the offset characteristic shown in figure 5 . fig 16. pca9521 bus multiplexer application driven from an i 2 c-bus i/o expander r1 1.1 k r2 1.1 k 3.3 v 002aaf293 scl sda sa1 sb1 en pca9521 v cc sa2 sb2 u2 scl pca9536 v dd io0 io1 u1 io2 io3 sda sa1 sb1 en pca9521 v cc sa2 sb2 u3 3.3 v multiple isolated buses with 400 pf load capacitance each i 2 c-bus i/o expander v offset v i 50 mv v bus r ------------ ?? ?? 11 ? ++ = v sa2 200 mv 50 mv 3.3 2000 ----------- - ?? ?? 11 268 mv = ? ++ = pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 13 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer 11. package outline fig 17. package outline sot96-1 (so8) unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18 pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 14 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer fig 18. package outline sot505-1 (tssop8) unit a 1 a max. a 2 a 3 b p lh e l p wy v ce d (1) e (2) z (1) references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.70 0.35 6 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot505-1 99-04-09 03-02-18 w m b p d z e 0.25 14 8 5 a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 1.1 pin 1 index pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 15 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer 12. handling information 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 16 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 19 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 5 and 6 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 19 . table 5. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 6. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 17 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. abbreviations 15. revision history msl: moisture sensitivity level fig 19. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 7. abbreviations acronym description atca advanced telecommunications computing architecture cdm charged-device model cpci compact peripheral component interconnect esd electrostatic discharge hbm human body model i 2 c-bus inter-integrated circuit bus ic integrated circuit ipmb intelligent platform management bus picmg pci industrial computer manufacturers group pmbus power management bus raid redundant array of independent discs smbus system management bus table 8. revision history document id release date data sheet status change notice supersedes pca9521 v.1 20110822 product data sheet - - pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 18 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. pca9521 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 22 august 2011 19 of 20 nxp semiconductors pca9521 fast dual bidirectional bus buffer non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors pca9521 fast dual bidirectional bus buffer ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 22 august 2011 document identifier: pca9521 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 7.1 v cc , gnd ? supply pins . . . . . . . . . . . . . . . . . 4 7.2 sa1, sa2, sb1, sb2 ? buffer inputs/outputs . 4 7.3 en ? enable; activate buffer operations . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 application information. . . . . . . . . . . . . . . . . . . 8 10.1 design considerations . . . . . . . . . . . . . . . . . . . 8 10.2 input to output offset voltage calculation . . . . 12 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 12 handling information. . . . . . . . . . . . . . . . . . . . 15 13 soldering of smd packages . . . . . . . . . . . . . . 15 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 15 13.2 wave and reflow soldering . . . . . . . . . . . . . . . 15 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 18 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17 contact information. . . . . . . . . . . . . . . . . . . . . 19 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 |
Price & Availability of PCA9521DP
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